For the most up to date list of publications, please check Google Scholar
Book Chapters
S.A. Hamza, K. Juretus, and M. Amin, “Sparse Array Design for Optimum Beamforming Using Deep Learning” In Sparse Arrays for Radar, Sonar, and Communications, M.G. Amin (Ed.), 2024.
Journal Publications
V. V. Rao, K. Juretus, and I. Savidis, “Hidden Costs of Analog Deobfuscation Attacks” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 11, pp. 1802-1815, Nov. 2023.
B. Lucas, A. Alwan, M. Murzello, Y. Tu, P. He, A. Schwartz, D. Guevara, U. Guin, K. Juretus, J. Xie, “Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator,” in IEEE Computer Architecture Letters, vol. 21, no. 1, pp. 17-20, June 2022.
M. Jacovic, K. Juretus, N. Kandasamy, I. Savidis, and K. R. Dandekar, “Physical Layer Encryption for Wireless OFDM Communication Systems,” Journal of Hardware and Systems Security, Vol. 4, pp. 230-245, July 2020.
K. Juretus and I. Savidis, “Increased Output Corruption and Structural Attack Resiliency for SAT Attack Secure Logic Locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 40, No. 1, pp. 38-51, Jan. 2021.
K. Juretus and I. Savidis, “Synthesis of Hidden State Transitions for Sequential Logic Locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 40, No. 1, pp. 11-23, Jan. 2021.
K. Juretus and I. Savidis, “Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, No. 8, pp. 1607-1620, Aug. 2020.
J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. R. Dandekar, “Securing Wireless Communication via Hardware-Based Packet Obfuscation,” Journal of Hardware and Systems Security, Vol. 3, No. 3, pp. 261-272, May 2019.
Conference Publications
J. Madera and K. Juretus. 2024. “Boolean Domain Attack on Corrupt and Correct Based Logic Locking Tech- niques,” Great Lakes Symposium on VLSI 2024 (GLSVLSI ’24), pp. 415–420, 2024.
K. Juretus, S. A. Hamza, and M. Amin, “Deep Learning-based Sparse Array Design for Emitter Signal Isolations,” Proc. SPIE 13036, Big Data VI: Learning, Analytics, and Applications, 130360H, June, 2024.
V. V. Rao, K. Juretus, and I. Savidis, “DNA: DC Nodal Analysis Attack for Analog Circuits,” IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, pp. 1-5, 2024.
M. G. Amin, S. A. Hamza, and K. Juretus, “Sparse Array Configuration Analysis and Deep Learning Classifications for Beamfornming,” IEEE Radar Conference, pp. 1-6, 2024.
S. A. Hamza, M. G. Amin, and K. Juretus, “On the Roles of Sparse Array Configuration and Weights in Optimum Beamforming,” IEEE Wireless Communications and Networking Conference (WCNC), pp. 1-6, 2024.
R. Wang, W. Wen, K. Juretus, and X. Jiao, “PP-HDC: A Privacy-Preserving Inference Framework for Hyper- dimensional Computing,” 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6, 2024.
S. A. Hamza, K. Juretus, M. G. Amin and F. Ahmad, “Deep Learning Sparse Array Design Considering Binary Switching and Missing Coarray Lags,” International Symposium on Signals, Circuits and Systems (ISSCS), pp. 1-4, 2023.
S. A. Hamza, K. Juretus, M. G. Amin and F. Ahmad, “Deep Learning Sparse Array Design Using Binary Switching Configurations,” ICASSP 2023 – 2023 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 1-5., 2023.
V. V. Rao, K. Juretus and I. Savidis, “Practical Performance of Analog Attack Techniques,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 153-156, June 2022.
K. Juretus and I. Savidis, “Reducing Logic Locking Key Leakage Through the Scan Chain,” Proceedings of the International Symposium on Circuits and Systems, pp. 1-5, October 2020.
V. Rao, K. Juretus and I. Savidis, “Security Vulnerabilities of Obfuscated Analog Circuits,” Proceedings of the International Symposium on Circuits and Systems, pp. 1-5, October 2020.
K. Juretus and I. Savidis, “Increasing the SAT Attack Resiliency of In-Cone Logic Locking,” Proceedings of the International Symposium on Circuits and Systems, pp. 1-5, May 2019.
K. Juretus, V. Rao, and I. Savidis, “Securing Analog Mixed-Signal Integrated Circuits Through Shared Depen- dencies,” Proceedings of the IEEE/ACM International Great Lakes Symposium on VLSI, pp. 483-488, May 2019.
K. Juretus and I. Savidis, “Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security,” Proceedings of the IEEE International Asia Pacific Conference on Circuits and Systems, pp. 366-369, October 2018.
D. Werner, K. Juretus, I. Savidis, and M. Hempstead, “Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures,” Proceedings of the IEEE International Conference on Computer Design, pp. 83-91, October 2018.
K. Juretus and I. Savidis, “Time Domain Sequential Locking for Increased Security,” Proceedings of the Interna- tional Symposium on Circuits and Systems, pp. 1-5, May 2018.
K. Juretus and I. Savidis, “Enhanced Circuit Security Through Hidden State Transitions,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference, pp. 781-784, March 2018.
J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. Dandekar, “Physical Gate Based Preamble Obfuscation for Securing Wireless Communication,” Proceedings of the International Conference on Com- puting, Networking and Communications, pp. 293-297, January 2017.
K. Juretus and I. Savidis, “Reducing logic encryption overhead through gate level key insertion,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1747-1717, May 2016.
K. Juretus and I. Savidis, “Reduced Overhead Gate Level Logic Encryption,” Proceedings of the IEEE/ACM International Great Lakes Symposium on VLSI, pp. 15-20, May 2016.
K. Juretus and I. Savidis, “Low Overhead Gate Level Logic Encryption,” Proceedings of the Government Micro- circuit Applications & Critical Technology Conference, pp. 455-459, March 2016.
Patents
M. Hempstead, D. Werner, E. Miller, K. Juretus, and I. Savidis, “Systems and methods for thermal side-channel analysis and malware detection” US Patent No. 11,880,463.
K. Juretus, V. Rao, and I. Savidis, “Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependen- cies,” US Patent No. 11,270,031.
J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. Dandekar, “Physical Layer Key Based Interleaving for Secure Wireless Communication,” US Patent No. 11,177,902.
V. Rao, I. Savidis, and K. Juretus, “Protecting Analog Circuits with Parameter Biasing Obfuscation,” US Patent No. 10,923,442.
J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. Dandekar, “Physical Gate Based Preamble Obfuscation for Securing Wireless Communication,” US Patent No. 11,177,902.
K. Juretus and I. Savidis, “Low Overhead Gate Level Logic Encryption,” US Patent No. 11,282,414.